CIQMoCA1

CIQMoCA1 is an IP solution for the MOCA 1.1 specification, initially targeted at the 65 nm LP process, which can be easily ported to newer technologies. CIQMoCA1 includes Verilog RTL source code, ANSI-C firmware source code, documentation, integration tests and support. Combined with an external Analog Front End provided by Analog Devices, the IP provides all mandatory and optional features of the MOCA 1.1 specification.

Features

        Autonomous Ethernet to MoCA bridge

        Fully MoCA 1.1 compliant

        E (mid) band (500-600MHz) or

D band (1150 to 1550 MHz) capable (requires the E/D band 9967 Analog Front End from Analog Devices)

        Supports packet aggregation, 256QAM Tx/Rx

        Flow Classification

        Single Tensilica LX3 processor

        Synopsys DesignWare DMA unit

        AHB bus interfaces

        No host system (DRAM) memory requirements

        Verilog

Performance

        Certified in 5 different ASICs from 3 different companies

        Meets all MoCA 1.1 CTP requirements

        Maximum PHY Rate > 270 Mbps

 


CIQMoCA2

Advance Information

CIQMoCA2 is an IP solution for the MOCA 2 specification targeted at the 40 nm process. CIQMoCA2 includes Verilog RTL source code, ANSI-C firmware source code, documentation, integration tests and support. Combined with an external Analog Front End, the IP provides all mandatory and optional features of the MOCA 2 specification.

Features

        Tensilica LX4 processor

        MoCA 2.0 Specification Compliant

        1024-QAM capable

        Channel Bonding

        Retransmission Reordering

        PQoS Policing

        Payload Concatenation

        packet aggregation

        Flow Classification

        AVB Support

        No host system (DRAM) memory requirements

Performance

        Maximum PHY Rate per Channel > 700 Mbps

        1024-QAM operation

        Meets all applicable MoCA 2.0 CTP requirements